f27084c6c0
soc/integration/cpu_interface: fix banner in get_mem_header
2019-04-24 22:44:37 +02:00
5ec99d94ae
Merge pull request #173 from gsomlo/gls-git-revision
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build: handle exceptional case when litex/migen not deployed as git repo
2019-04-24 22:42:36 +02:00
d21cba2f17
build: handle exceptional case when litex/migen not deployed as git repo
2019-04-24 12:50:47 -04:00
27fbb814ab
tools/remote/csr_builder: allow comments in csv file and cleanup
2019-04-24 12:25:49 +02:00
e8f3c49127
software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding
2019-04-24 11:32:40 +02:00
44e0cdda9a
software/libnet/microudp: speed-up ARP by changing timeout/tries
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First ARP request does not seem to be transmitted (the link is probably not
fully established). Reduce the timeout between tries and increase number of
tries.
2019-04-24 09:55:41 +02:00
3ee78a5b70
build/tools: fix typo
2019-04-23 18:10:51 +02:00
f0fe9f3cdf
setup.py: add short names for tools
2019-04-23 17:46:20 +02:00
9ded2eb20b
tools/litex_term: change TERM prompt to LXTERM
2019-04-23 17:46:02 +02:00
475deb51ac
build: add migen and litex git revision to generated file
2019-04-23 17:40:24 +02:00
8b5cf29542
build/tools: git_revision is not doing what we want, return "--------" for now
2019-04-23 17:15:43 +02:00
228f286747
litex_setup: revert default install behaviour but add --user support
2019-04-23 14:53:00 +02:00
9fbbf928ed
Merge pull request #171 from keesj/develop_as_user
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Install development packages in the user directory
2019-04-23 14:41:37 +02:00
0f60ec35e2
tools/litex_server: fix comms import
2019-04-23 14:25:27 +02:00
68f12495cf
soc/integration: also add sha-1/date to generated software files
2019-04-23 13:17:54 +02:00
425741226c
build: add sha-1/date to generated verilog, change git_version to git_revision
2019-04-23 12:59:25 +02:00
24bdb6487d
Install development packages in the user directory
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When in development mode install the packages in the user directory using the
--user flag from pip. This allows to install and run without the need for root
access.
2019-04-23 12:23:09 +02:00
f7c0b118ce
test/test_targets: cover all platforms
2019-04-23 11:38:18 +02:00
818dfae1e8
boards/platforms/ulx3s: fix default clock
2019-04-23 11:37:29 +02:00
17b6164cd9
boards/platforms/sp605: apply same simplifications than on others platforms
2019-04-23 11:21:55 +02:00
24bf02934e
boards/platforms: add SP605
2019-04-23 11:15:42 +02:00
10cf0fdea3
cores/cpu/vexriscv: fix wrong revert
2019-04-23 11:13:29 +02:00
d2ad14417a
targets/ac701: cleanup and make it similar to others targets.
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Still supports EthernetSoC with RGMII and 1000BaseX.
2019-04-23 11:10:35 +02:00
a24bf72fc7
targets/xilinx: remove keep attribute on clock going to idelayctrl
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Causes P&R issues with Vivado.
2019-04-23 10:51:36 +02:00
ea8dbff86e
boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms
2019-04-23 10:50:19 +02:00
0122982e09
boards/platforms/kc705: provide only one default programmer as others platforms
2019-04-23 10:00:52 +02:00
89a590263f
boards: Xilinx ac701 dev board support
2019-04-23 09:48:16 +02:00
88b882c7e0
build/xilinx/ise.py: write .v file for post synthesis sim
2019-04-23 09:22:48 +02:00
7396ebbb38
build/xilinx/programmer: cleanup XC3SProg position parameter
2019-04-23 09:20:59 +02:00
f579cbc603
build/xilinx/programmer: add position parameter to XC3SProg
2019-04-23 09:16:42 +02:00
fb4f881857
.gitignore: ignore tilde files
2019-04-23 09:10:11 +02:00
535d86727a
targets/minispartan6: use S6PLL in CRG
2019-04-23 06:44:29 +02:00
40342404f2
cores/clock: add divclk_divide_range on S6PLL/S6DCM
2019-04-23 06:43:48 +02:00
0d282f38f9
cores/clock: use common XilinxClocking class for all Xilinx clocking modules
2019-04-23 06:35:39 +02:00
83699ea0a5
cores/clock: add initial Spartan6 PLL/DCM support
2019-04-23 06:23:00 +02:00
eff141da2d
build: add git version (sha-1) used to create the scripts
2019-04-23 06:03:12 +02:00
cc141a64b9
build: scripts are generated by LiteX
2019-04-23 05:38:33 +02:00
115c842ef0
build/xilinx/vivado: cleanup pull request #170
2019-04-23 05:33:56 +02:00
3b24b8d5b4
Merge pull request #170 from ldoolitt/master
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build/xilinx/vivado: only try Xilinx setup if vivado is not already i…
2019-04-23 05:26:54 +02:00
fda18fd6ef
build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path
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Only affects the non-Windows code path.
Uses python distutils, already used elsewhere.
2019-04-22 15:42:31 -07:00
7d278854d5
global: switch to VexRiscv as the default CPU
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VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
2019-04-22 09:41:07 +02:00
28d80bd641
ci: fix test_targets/test_simple
2019-04-22 08:53:43 +02:00
b7f53fb93c
test: remove waveforms generation
2019-04-22 08:41:28 +02:00
e98ac680c1
travis: simplify, enable and add RISC-V toolchain to build targets
2019-04-22 08:32:00 +02:00
8c78997089
boards/platforms: add separators, cleanup imports
2019-04-21 00:44:23 +02:00
cb8c26d1b8
boards/platforms: provide only one default programmer per platform.
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create_programmer is not really longer used, so try to keep it simple.
2019-04-21 00:17:03 +02:00
e1d202df02
boards/platforms/kc705: only keep Vivado support
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There is no reason still using ISE on 7-Series.
2019-04-21 00:04:56 +02:00
53c7be6e46
boards: always define timing constraints the same way (1e9/freq_mhz)
2019-04-20 23:56:27 +02:00
02ffbed5e3
boards/targets/ulx3s: allow running test_targets on it
2019-04-20 23:47:05 +02:00
5a1925df2e
boards/targets: add keep attribute directly in crg
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This makes it systematic and avoid having to add it later.
2019-04-20 23:43:44 +02:00
Florent Kermarrec
Gabriel L. Somlo
Kees Jongenburger
Michael Betz
Vamsi K Vytla
Larry Doolittle