Florent Kermarrec
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b75b93df43
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misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.
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2015-07-24 14:05:54 +02:00 |
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Florent Kermarrec
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d73d75007e
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misoclib/com/uart: cleanup and add irq condition parameters
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
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2015-07-24 12:57:42 +02:00 |
Robert Jordens
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a501d7c52d
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uart: support async phys
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2015-07-19 23:37:00 +02:00 |
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Florent Kermarrec
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8aa3fb3eb7
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com/uart: add tx and rx fifos.
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
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2015-05-01 15:59:26 +02:00 |
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Florent Kermarrec
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f68423f423
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global: pep8 (E302)
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2015-04-13 16:47:22 +02:00 |
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Florent Kermarrec
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d9e09707ae
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global: pep8 (replace tabs with spaces)
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2015-04-13 16:19:55 +02:00 |
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Florent Kermarrec
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200791c81d
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uart: generate ack for rx (serialboot OK with sim)
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2015-03-04 00:57:37 +01:00 |
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Florent Kermarrec
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f58394f6af
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soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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2015-03-01 18:25:47 +01:00 |
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Florent Kermarrec
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096e95cb59
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uart: use data instead of d on endpoint's layouts (coherency with others cores)
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2015-03-01 16:56:48 +01:00 |
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Florent Kermarrec
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bd4d3cd73b
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uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
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Florent Kermarrec
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2c51adcd68
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misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |