20 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	f35cd4a85b	Prepare for new DDR PHY	2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq	026457a98c	Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.	2012-02-18 18:12:14 +01:00
Sebastien Bourdeauducq	5bc840b9c1	DFI injector (untested)	2012-02-17 23:50:10 +01:00
Sebastien Bourdeauducq	c387ce7ce5	Map DDR PHY controls in CSR	2012-02-17 17:34:59 +01:00
Sebastien Bourdeauducq	5d1dad583b	Connect DDR PHY ... Doesn't do much for the moment, just to check synthesis/P&R.	2012-02-17 11:04:44 +01:00
Sebastien Bourdeauducq	72f9af9d90	Generate all clocks for the DDR PHY	2012-02-16 18:02:37 +01:00
Sebastien Bourdeauducq	5165ff7ec3	Include Wishbone to ASMI bridge	2012-02-13 23:12:57 +01:00
Sebastien Bourdeauducq	58f4f78d2c	sram: fix sub-word write	2012-02-06 23:13:35 +01:00
Sebastien Bourdeauducq	33f1c456bf	top: connect UART IRQ	2012-02-06 17:45:40 +01:00
Sebastien Bourdeauducq	9b9a510525	Memory map	2012-02-05 19:54:08 +01:00
Sebastien Bourdeauducq	28f00c3a9a	Add on-chip SRAM	2012-01-27 22:09:03 +01:00
Sebastien Bourdeauducq	6fde54c5aa	Use meaningful class names	2012-01-21 12:25:22 +01:00
Sebastien Bourdeauducq	f6aa95a4d0	Use new verilog.convert API	2012-01-20 23:00:11 +01:00
Sebastien Bourdeauducq	570ea8ccf8	convtools -> tools	2012-01-13 17:07:46 +01:00
Sebastien Bourdeauducq	b60abfaa4a	Convert -> convert	2012-01-05 19:27:45 +01:00
Sebastien Bourdeauducq	6664af73d1	uart: new design using FHDL and bank (TX only, incomplete)	2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq	0e30d67fa3	Multiply system clock	2011-12-17 15:00:18 +01:00
Sebastien Bourdeauducq	411e1af980	Proper reset generation	2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq	ca68097ef6	Pay a bit more attention to PEP8	2011-12-16 16:02:49 +01:00
Sebastien Bourdeauducq	b487e99bcf	Initial import	2011-12-13 17:33:12 +01:00