13fb9282db
targets: add simple design (vendor agnostic and usable on all platforms with UART pins).
...
Designing a SoC with Migen is easy, but we have to provide a very simple design that can
be used on all boards with only 1 clock and 2 UARTs pins defined. This will encourage the
newcomer to invest time in Migen/MiSoC and see its real potential.
2014-09-26 10:35:15 +08:00
1d053bd7ee
modify TestDesign to be able to simulate phy with host <--> device loopback
2014-09-25 15:37:49 +02:00
7e14c4fc51
move some logic outside of GTX
2014-09-25 15:23:56 +02:00
c008dfdd98
clean up (thanks to Sebastien)
2014-09-25 14:17:25 +02:00
111f527647
do some clean up
2014-09-24 22:26:33 +02:00
2fb418a373
use new MiSoC UART with phase accumulators
...
this will allow to speed up MiLa reads
2014-09-24 21:56:15 +02:00
435bc22fa0
integrate phy in test design and start fix syntax errors
2014-09-24 16:07:34 +02:00
18009303ae
instanciate device or host controller
2014-09-24 14:00:00 +02:00
60324295fa
manage clock domain crossing and data width conversion in gtx
2014-09-24 13:56:12 +02:00
f436069a04
create sata clock (sata_tx/2 for a 32 bits data path)
2014-09-24 13:55:06 +02:00
7790105913
realign rxdata / rxcharisk directly in gtx
2014-09-24 12:13:43 +02:00
f74471d027
add device ctrl skeleton (we will use it for simulation with the host)
2014-09-24 11:37:28 +02:00
d78cae1b57
more ctrl skeleton
2014-09-24 11:07:36 +02:00
71bfd036d0
add ctrl skeleton
2014-09-24 00:01:01 +02:00
fa509b3365
rearrange code and remove datapath for now
2014-09-23 23:03:32 +02:00
22ea5b08b0
clean up and add K7SATAGTXReconfig skeleton (empty but we don't need it for now)
2014-09-23 22:40:01 +02:00
674e0b3581
remove GTXE2_COMMON (we use in fact CPLL and not QPLL, GTXE2_COMMON was here in design just because of an old ISE bug)
...
(see http://www.xilinx.com/support/answers/45410.html for more information)
2014-09-23 22:17:08 +02:00
e0fd313ce0
add data path from another design (need to be adapted to SATA specification)
2014-09-23 17:36:11 +02:00
d55db1688b
add SATAGTX with RX/TX clocking and reset (no DRP for now)
2014-09-23 17:18:03 +02:00
410f250d2a
software: remove setjmp
2014-09-23 21:57:05 +08:00
cbbbf8de8b
add dict for fbdiv computation on GTXE2_COMMON
2014-09-23 14:11:14 +02:00
4aff15bb74
create k7satagtx.py and move GTXE2 primitive inside
2014-09-23 14:03:51 +02:00
7422b94f90
create GTXE2_CHANNEL & GTXE2_COMMON class / add IO signals and parameters
2014-09-23 13:57:02 +02:00
1a5a2d10e3
fill GTXE2_COMMON constants parameters and signals for SATA / disconnect unused output ports
2014-09-23 12:01:57 +02:00
fc64b44391
fill GTXE2_CHANNEL constants parameters and signals for SATA / disconnect unused output ports
2014-09-23 11:54:36 +02:00
ac8d8783cf
k7sataphy: add GTXE2_COMMON instance skeleton
2014-09-23 10:23:54 +02:00
bdf038f241
k7sataphy: add GTXE2_CHANNEL instance skeleton
2014-09-23 10:08:17 +02:00
a03570ccca
flow/actor: fix eop direction
2014-09-23 00:14:58 +08:00
66054af7bb
flow/actor: add packetized parameter for Sink and Source
2014-09-22 23:45:28 +08:00
967b73bef3
actorlib/structuring: add reverse parameter to Unpack and Pack
2014-09-22 23:41:40 +08:00
7e31ef2152
init with repo with simple TestDesign
2014-09-22 13:36:43 +02:00
14d53526be
libbase: use __builtin_setjmp and __builtin_longjmp
2014-09-21 17:43:17 +08:00
6c9810532b
genlib/fifo/SyncFIFOBuffered: replace not supported
2014-09-17 19:59:13 +08:00
4cacf97088
genlib/fifo: same 'level' semantics between SyncFIFOBuffered and FWFT SyncFIFO
2014-09-17 19:58:43 +08:00
503a2f00b5
mor1kx: sync
2014-09-12 16:00:32 +08:00
09ebcc47aa
setup.py: fix README filename
2014-09-12 08:19:05 +08:00
264bc61e04
genlib/fifo: add replace command to sync FIFO
2014-09-10 21:19:15 +08:00
b15c357a10
README: more markdown fixes
2014-09-10 20:52:19 +08:00
4bdc550924
README: markdown fixes
2014-09-10 20:51:17 +08:00
92e51f10b1
README: use markdown
2014-09-10 20:49:49 +08:00
325ffdc6c6
actorlib/spi: remove unneeded import
2014-09-08 18:48:54 +08:00
c1e12c3346
actorlib/spi: remove EventManager from DMAController
2014-09-08 11:34:21 +08:00
0bac463780
sim/icarus: add vpi directory to module search path
...
This allows running the iverilog simulations from the migen top directory
without having to install the .vpi anywhere.
2014-09-07 16:49:12 +08:00
3d84a7a9de
cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic
2014-09-07 16:49:12 +08:00
11f58862db
test_cordic: stop spewing out numbers
2014-09-07 16:49:12 +08:00
11fedfc825
doc: update for NetworkX refactoring
2014-09-07 16:48:46 +08:00
7518a7b0c0
examples/dataflow: adapt to new simple MultiDiGraph implementation
2014-09-07 16:48:46 +08:00
4def6ec391
flow/network: replace NetworkX MultiDiGraph with simple implementation
2014-09-07 16:48:46 +08:00
8489604142
examples/dataflow/dma: fix simulation, run it for 100 cycles
2014-09-07 16:48:46 +08:00
683643266f
cordic: vivado is bad at inferring compact adder/subtractor logic
2014-09-04 15:25:34 +08:00
Florent Kermarrec
Sebastien Bourdeauducq
Robert Jordens