dc8d844579
liteusb: begin refactoring and simplification (wip)
2015-04-27 15:22:49 +02:00
3ce5ff3722
migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer)
2015-04-27 15:14:38 +02:00
f976b1916a
migen/actorlib/misc: add BufferizeEndpoints
...
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
2015-04-27 15:12:01 +02:00
e96ba1e46f
migen/genlib/misc: add reverse_bytes
2015-04-27 15:08:10 +02:00
91c77d464c
liteeth: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:06:37 +02:00
20dd6d3047
litepcie: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:05:40 +02:00
1ef81c4d24
litesata: split hdd model (phy, link, transport, command & hdd) and update simulations
2015-04-27 14:51:03 +02:00
ded3f22574
litesata: use new Migen modules from actorlib/packet.py (avoid duplications between cores)
2015-04-27 14:48:14 +02:00
fe867ccf33
litesata: remove icarus_workaround.patch (obsolete)
2015-04-27 14:44:54 +02:00
1d9771f574
spiflash: use SoC defines, add write_to_flash function
2015-04-27 13:42:32 +08:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
07b7c2a13f
liteeth/phy/gmii: add default value for pads_register
2015-04-26 14:54:54 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
472665b81d
Add a command line option (-use_new_parser yes) to Xilinx XST to force use of the newer parser for older FPGAs.
2015-04-25 23:01:07 +08:00
73a1687562
migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?)
2015-04-24 13:24:52 +02:00
67702f25ab
migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb)
2015-04-24 12:54:08 +02:00
bc30fc57e7
migen/fhdl: give explicit names to syntax specialization when asic_syntax is used
2015-04-24 12:14:14 +02:00
61c3efc5f5
migen/test: rename asic_syntax to test_syntax and simplify
2015-04-24 12:00:46 +02:00
130fd19dec
liteeth/core/ip: simplify ip rx checksum control
2015-04-24 11:31:10 +02:00
5b48e7bb52
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
2015-04-24 11:30:35 +02:00
2d56d32009
liteeth/mac/core: simplify and fix padding
2015-04-24 09:36:33 +02:00
b93df693a4
travis: add conda package generation and upload + build doc
2015-04-23 14:15:31 +08:00
7280bdb9d4
Add conda recipe for Migen
2015-04-23 14:15:15 +08:00
2f45d4640b
doc: fix warnings during doc build
2015-04-23 12:34:17 +08:00
e5b170f02d
travis: install verilator
2015-04-22 12:30:03 +08:00
7ec0ecae11
test: add test for asic_syntax
2015-04-22 12:29:07 +08:00
6b5969732a
add Travis CI badge
2015-04-22 12:20:46 +08:00
28dde1e38f
fhdl/verilog: add flag to produce ASIC-friendly output
2015-04-21 09:52:14 +08:00
b8bbaaef3a
Fixing shadowing of global index function.
...
Fixes the following warnings;
```
cc -Wall -O2 -fPIC -Wall -Wshadow -g -O2 -fstack-protector --param=ssp-buffer-size=4 -Wformat -Wformat-security -I/usr/include/iverilog -c -o ipc.o ipc.c
ipc.c: In function ‘ipc_receive’:
ipc.c:98:17: warning: declaration of ‘index’ shadows a global declaration [-Wshadow]
ipc.c:113:17: warning: declaration of ‘index’ shadows a global declaration [-Wshadow]
```
Fixes https://github.com/m-labs/migen/issues/14
2015-04-21 00:26:07 +08:00
f57ee296a9
mibuild/altera: cleanup
2015-04-20 17:17:34 +08:00
65eeb33329
Revert "add I/O standard definitions to mibuild/altera"
...
This reverts commit a889b41060
2015-04-20 16:22:32 +08:00
a889b41060
add I/O standard definitions to mibuild/altera
2015-04-20 10:08:47 +02:00
1b050d98ea
add differential in/out support to mibuild/altera
2015-04-20 10:08:26 +02:00
fd966d70ba
some PEP8 cosmetic
2015-04-20 10:03:08 +02:00
ff2d1d9383
litescope: fix read in reg.py
2015-04-20 08:16:31 +02:00
4c0d9f5f36
litescope: remove repeat mode on drivers (not useful) and cleanup
2015-04-18 15:37:38 +02:00
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
341f635a85
litescope: add PCIe driver (mmap/Sysfs) and use it on litepcie example design
2015-04-18 13:58:20 +02:00
602eaf69c7
litepcie: fix asciiart in make.py
2015-04-17 14:10:32 +02:00
8a822b9deb
litepcie: add litepcie_phy_wrappers to extcores
2015-04-17 13:52:21 +02:00
b4b37fb10e
litepcie: add linux driver + utilities (sysfs + dma)
2015-04-17 13:48:34 +02:00
d22d58c7cc
add litepcie core
2015-04-17 13:45:01 +02:00
93de581931
soc: add shadow_address parameter
...
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
2015-04-17 13:42:29 +02:00
9666629c4f
soc/cpuif: add with_access_functions parameter
...
When don't necessary need access functions in our csr.h (for example with an X86 CPU)
2015-04-17 13:26:38 +02:00
15625236c1
platforms/kc705: add PCIe pins
2015-04-17 00:51:16 +02:00
083d371af4
mibuild: add support for libraries, move .replace("\\", "/") to generic_platform.py and execute it only on Windows machines.
...
We need to support libraries when Migen is used as a wrapper on large VHDL designs using libraries.
2015-04-17 00:11:31 +02:00
958f149992
litesata/test: fix PYTHONPATH
2015-04-16 19:49:46 +08:00
ae503bc7b9
travis: disable email notification
2015-04-14 23:45:33 +08:00
9c8c20341f
travis: add IRC notification
2015-04-14 23:30:52 +08:00
9e7dc175a4
Using a newer version of iverilog.
2015-04-14 23:17:13 +08:00
Florent Kermarrec
Sebastien Bourdeauducq
William D. Jones
Yann Sionneau
Guy Hutchison
Alain Péteut
Tim 'mithro' Ansell