Sebastien Bourdeauducq
|
0b62e573ae
|
sim: pass extra keyword arguments to Verilog converter
|
2012-04-30 16:38:17 -05:00 |
|
Sebastien Bourdeauducq
|
2a4e49e381
|
fhdl: phase out pads
|
2012-04-02 19:21:43 +02:00 |
|
Sebastien Bourdeauducq
|
f6e76ae198
|
doc: more examples and comments
|
2012-03-10 19:38:39 +01:00 |
|
Sebastien Bourdeauducq
|
1f4c58ee26
|
doc: cosmetic changes (thanks sh4rm4 for reporting typos)
|
2012-03-10 17:59:42 +01:00 |
|
Sebastien Bourdeauducq
|
78c707e354
|
doc: use script font
|
2012-03-09 21:57:50 +01:00 |
|
Sebastien Bourdeauducq
|
7b1101ab99
|
doc: simulation
|
2012-03-09 21:17:21 +01:00 |
|
Sebastien Bourdeauducq
|
0165d23295
|
doc: cosmetic changes (thanks rofl0r for reporting typos)
|
2012-03-09 18:26:00 +01:00 |
|
Sebastien Bourdeauducq
|
90546fd811
|
doc: switch to sphinx
|
2012-03-09 17:08:38 +01:00 |