8d1c555e36
misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.
...
An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth.
For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.
2015-07-25 00:25:09 +02:00
b75b93df43
misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.
2015-07-24 14:05:54 +02:00
d73d75007e
misoclib/com/uart: cleanup and add irq condition parameters
...
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
2015-07-24 12:57:42 +02:00
a501d7c52d
uart: support async phys
2015-07-19 23:37:00 +02:00
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
f68423f423
global: pep8 (E302)
2015-04-13 16:47:22 +02:00
d9e09707ae
global: pep8 (replace tabs with spaces)
2015-04-13 16:19:55 +02:00
200791c81d
uart: generate ack for rx (serialboot OK with sim)
2015-03-04 00:57:37 +01:00
f58394f6af
soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
2015-03-01 18:25:47 +01:00
096e95cb59
uart: use data instead of d on endpoint's layouts (coherency with others cores)
2015-03-01 16:56:48 +01:00
bd4d3cd73b
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
2015-03-01 12:14:34 +01:00
2c51adcd68
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
Florent Kermarrec
Robert Jordens