7e53bff39d
litex_setup: add litesata
2019-04-10 18:04:48 +02:00
792245f196
boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter)
2019-04-10 16:36:49 +02:00
f8dcdb70d2
software/libnet: add #ifdef on eth_init
2019-04-10 16:16:47 +02:00
e475cfbb7d
Merge pull request #158 from vbuitvydas/altera-contrib
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Changes for litepcie support for Altera Cyclone V
2019-04-08 14:32:44 +02:00
04939990ac
litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name
2019-04-08 14:07:10 +03:00
8558065fca
litex/build/altera/common: added reset synchronizer
2019-04-08 14:06:24 +03:00
866fa34493
integration/soc_zynq: fix missing SoCCore.do_finalize
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Signed-off-by: Florent Kermarrec <florent@enjoy-digital.fr>
2019-04-01 14:44:37 +02:00
794c3c5860
integration/soc_zynq: add add_hp0 method
2019-04-01 11:10:35 +02:00
38d404c3cb
integration/soc_zynq: use add methods to add optional peripherals
2019-04-01 10:50:04 +02:00
7375856bec
integration/soc_zynq: connect axi signals that were missing
2019-04-01 10:31:33 +02:00
b15fd9d834
interconnect/axi: add missing axi signals
2019-04-01 10:23:25 +02:00
f95748d167
Merge pull request #157 from CBJamo/master
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Add ifdef check for MAIN_RAM_SIZE
2019-03-31 18:46:07 +02:00
1f0b3f8124
Add ifdef check for MAIN_RAM_SIZE
2019-03-31 10:33:39 -05:00
f452d3e96f
README: bump copyright year
2019-03-30 12:27:06 +01:00
dd214d2d21
bios/main: align SoC info, show CPU speed on CPU line, show L2
2019-03-30 11:49:39 +01:00
6599f7bb50
bios/main: move sdrinit
2019-03-30 10:56:17 +01:00
b92b89ab92
bios/main: print boot sequence only if sdr_ok
2019-03-30 10:19:00 +01:00
f4369c8fb2
bios/main: remove csr functions (not used and only supported by lm32), improve help presentation
2019-03-29 19:40:24 +01:00
66dffb7071
software/bios: improve readibility, add soc informations
2019-03-29 00:51:16 +01:00
e8559990b6
Merge pull request #156 from gsomlo/gls-axi-width
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soc/interconnect/axi: address length cleanup
2019-03-28 18:27:36 +01:00
449632e430
soc/interconnect/axi: data/address length cleanup
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Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
2019-03-27 16:52:52 -04:00
552b0243b3
soc/interconnect/axi: remove dead code (thanks gsomlo)
2019-03-27 21:15:14 +01:00
b682dacdd7
Merge pull request #154 from daveshah1/yosys_xilinx_edif
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build/xilinx: Update Yosys write_edif parameters
2019-03-22 17:43:40 +01:00
57e1ccd5f8
build/xilinx: Update Yosys write_edif parameters
2019-03-22 16:06:52 +00:00
fd7ed6c1ec
utils/litex_sim: fix main_ram_size
2019-03-16 21:25:02 +01:00
3f386dad7d
soc_core/get_mem_data: add json support
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example of json file:
{
"vmlinux.bin": "0x00000000",
"vmlinux.dtb": "0x01000000",
"initramdisk.gz": "0x01002000"
}
2019-03-16 21:23:36 +01:00
7bc13ba841
build/microsemi/libero_soc: add linux build script support
2019-03-16 09:33:16 +01:00
7b88980d06
vexriscv: allow user to use an external variant
2019-03-15 18:16:25 +01:00
b04a756abb
vexriscv/core: fix min variant
2019-03-15 17:49:39 +01:00
a549f0941b
utils/litex_sim: handle cpu_endianness for rom-init/ram-init
2019-03-13 10:56:09 +01:00
411bca790a
utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified
2019-03-13 10:42:10 +01:00
7ec3ed4d89
Merge pull request #153 from railnova/fix_utils
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[fix] utils was omitted when installed from pip
2019-03-07 21:12:00 +01:00
aed2e9b4b5
[fix] utils was not installed from pip
2019-03-07 09:40:58 +01:00
3543b56753
Merge pull request #152 from gsomlo/gls-trellis-svf
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build/lattice/trellis: generate bitstream directly in svf format
2019-03-06 23:41:20 +01:00
b014c7194b
build/lattice/trellis: also generate bitstream in svf format
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Before being able to program the board (e.g., with openocd), one
would have to convert the bitstream file to .svf using a python
script included with the source trellis distribution. However,the
trellis 'ecppack' utility can also generate .svf bitstream files
directly.
2019-03-06 16:29:18 -05:00
317dba8314
software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation
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In the future, the PHYs should generated these constants.
2019-03-05 18:03:24 +01:00
7de1fe519a
targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC
2019-03-05 13:27:11 +01:00
ca63db4040
bios/sdram: use burstdet detection for ECP5DDRPHY init
2019-03-05 13:27:06 +01:00
2ebfab5e1f
Merge pull request #150 from daveshah1/trellis_bus_fixes
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lattice/common: Fix tristate buses with Trellis
2019-03-04 12:00:44 +01:00
ebe8f600e1
lattice/common: Fix tristate buses with Trellis
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 10:50:56 +00:00
935f3a5337
boards/ulx3s: add device selection parameter
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ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F
2019-03-04 09:40:14 +01:00
e6f97e08d2
targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25
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Now supported by Trellis/Nextpnr.
2019-03-04 09:27:31 +01:00
5ef28bdf75
build/lattice/trellis: add package support
2019-03-01 15:20:02 +01:00
1b34c07da9
build/lattice/trellis: basecfg now integrated in nextpnr
2019-03-01 14:20:00 +01:00
7e995eb418
boards/targets/ulx3s: allow building with diamond or trellis
2019-03-01 13:59:28 +01:00
4bf789eab9
soc/software/bios/boot: add vexriscv workaround
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Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
2019-03-01 09:16:48 +01:00
1fd81c2882
soc/integration: add initial SoCZynq SoC
2019-02-27 22:39:35 +01:00
3c527dcbdf
soc/interconnect: add initial axi code with bus definition and AXI2Wishbone
2019-02-27 22:26:57 +01:00
ed2578799b
test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
2019-02-27 22:24:56 +01:00
4aa07f2ae9
soc/interconnect: rename axi to axi_lite
2019-02-27 22:11:09 +01:00
Florent Kermarrec
vytautasb
Caleb Jamison
Gabriel L. Somlo
David Shah
chmousset