Commit Graph

111 Commits

Author SHA1 Message Date
Florent Kermarrec a5ed42ec68 soc/interconnect/stream: add Gearbox 2018-11-17 17:29:45 +01:00
Florent Kermarrec 11d536dc4d test: remove test_bitslip (integrated in migen) 2018-11-17 17:29:09 +01:00
Florent Kermarrec 0b0e3ac1dd test/test_targets: test simple design with all platforms 2018-09-24 02:02:14 +02:00
Florent Kermarrec e04530e0c4 test/test_targets: update and reorganize targets 2018-09-24 01:15:33 +02:00
Florent Kermarrec 1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Florent Kermarrec e0ce485a17 test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules) 2017-04-25 10:57:34 +02:00
Florent Kermarrec 3ca0cb0cea test: add test_gearbox skeleton 2017-04-24 21:41:46 +02:00
Florent Kermarrec b4ebfb4031 test/test_targets: check top.v generation 2017-04-24 19:25:58 +02:00
Florent Kermarrec 35e3d93d9b test: add basic test_targets.py 2017-04-24 19:13:17 +02:00
Florent Kermarrec dc66dfcb55 test: add test_bitslip (initially in litedram) 2017-04-24 18:50:06 +02:00
Florent Kermarrec 96898f1b39 add test directory with test_code_8b10b.py (from misoc) 2017-04-24 18:46:55 +02:00