7 commits

Author	SHA1	Message	Date
Florent Kermarrec	f58394f6af	soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)	2015-03-01 18:25:47 +01:00
Florent Kermarrec	bd4d3cd73b	uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)	2015-03-01 12:14:34 +01:00
Florent Kermarrec	144ee7ea9f	soc: fix register_rom	2015-02-28 23:51:51 +01:00
Florent Kermarrec	5c43d4d091	litescope: create example design derived from SoC that can be used on all targets	2015-02-28 22:19:24 +01:00
Florent Kermarrec	165a5b6760	soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000	2015-02-28 20:04:51 +01:00
Florent Kermarrec	8564b7eb6a	soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)	2015-02-28 11:44:14 +01:00
Florent Kermarrec	69e869893d	remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)	2015-02-28 11:36:15 +01:00

Renamed from misoclib/gensoc/__init__.py (Browse further)