litex/litex
Gwenhael Goavec-Merou 7f7e44646d build/xilinx/yosys_nextpnr.py: fix device name for xc7a35ticsg324-1L & xc7a200t-sbg484-1 (as done for f4pga) 2024-04-19 06:57:01 +02:00
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build build/xilinx/yosys_nextpnr.py: fix device name for xc7a35ticsg324-1L & xc7a200t-sbg484-1 (as done for f4pga) 2024-04-19 06:57:01 +02:00
compat compat/soc_core: Fix register_mem/rom missing imports. 2022-11-09 19:11:15 +01:00
gen sim/gtkwave: Update/fix SignalNamespace import (And make it public in fhdl/namer). 2023-11-09 10:29:43 +01:00
soc Revert "Uart tx irq handling fix " (issue #554) 2024-04-16 14:01:38 +02:00
tools tools/litex_term: Minor cosmetic changes. 2024-04-18 15:09:24 +02:00
__init__.py colorer: Avoid duplication and move it to litex/gen. 2022-11-03 09:49:51 +01:00