enjoy-digital 3041150773 Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special ... build/altera/common,platform: added ddrinput/ddrout primitives		2024-07-26 18:26:19 +02:00
..
build	Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special	2024-07-26 18:26:19 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	global: Remove @trabucayre's tracers :)	2024-07-26 12:57:01 +02:00
tools	tools/litex_sim: Cleanup imports.	2024-07-18 12:16:23 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00