Florent Kermarrec d4d1a1bfd7 gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.		2024-07-03 21:44:31 +02:00
..
fhdl	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
genlib	gen/genlib/misc/WaitTimer: Cast t to int and minor cosmetic cleanup.	2023-07-31 11:27:47 +02:00
sim	gen/fhdl/namer: Use _ for private functions and remove build_namespace.	2023-11-06 16:21:33 +01:00
__init__.py	litex/gen: Split common in common/context/reduce/signal.	2023-07-27 15:02:37 +02:00
common.py	litex/gen/common: Add short and long byte size definitions.	2024-06-13 09:54:20 +02:00
context.py	gen/context: Rename soc to top.	2023-11-03 11:05:57 +01:00
reduce.py	litex/gen: Split common in common/context/reduce/signal.	2023-07-27 15:02:37 +02:00
signal.py	litex/gen: Add some comments.	2023-07-27 16:18:30 +02:00