Florent Kermarrec 42cf2ca5d0 gen/fhdl/namer: Return Non if sig is None.		2024-12-02 17:27:05 +01:00
..
__init__.py	litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented	2015-11-13 14:44:16 +01:00
hierarchy.py	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
instance.py	gen/fhdl/instance: Ident Parameters/IOs on max length of names.	2023-11-03 12:31:14 +01:00
memory.py	gen/fhdl/memory: Rename memory_emit_verilog to _memory_generate_verilog.	2023-11-03 11:29:48 +01:00
module.py	gen/fhdl/module: Ensure Module/Special/ClockDomains are initialized before adding them as submodules/specials/clock_domains.	2023-10-27 12:26:54 +02:00
namer.py	gen/fhdl/namer: Return Non if sig is None.	2024-12-02 17:27:05 +01:00
verilog.py	gen/fhdl/verilog: Ensure top is not None to build hierarchy.	2023-11-08 16:58:23 +01:00