Sebastien Bourdeauducq 009f26bb9d flow/network: refactor graph		2012-06-08 22:49:49 +02:00
..
basic2_sim.py	Update copyright notices	2012-03-23 16:41:30 +01:00
basic_sim.py	Update copyright notices	2012-03-23 16:41:30 +01:00
corelogic_conv.py	Use meaningful class names	2012-01-20 23:07:32 +01:00
dataflow.py	flow/network: refactor graph	2012-06-08 22:49:49 +02:00
dataflow_dma.py	flow/network: refactor graph	2012-06-08 22:49:49 +02:00
dataflow_sim.py	flow/network: refactor graph	2012-06-08 22:49:49 +02:00
fir.py	examples/fir: print Verilog source	2012-06-08 14:00:49 +02:00
fsm.py	Use double quotes for all strings	2012-02-14 13:12:43 +01:00
lm32_inst.py	fhdl: support forwarding of bidirectional signals from instance ports	2012-02-16 18:34:32 +01:00
memory.py	fhdl: support memory read enable	2012-01-27 21:39:23 +01:00
memory_sim.py	Update copyright notices	2012-03-23 16:41:30 +01:00
simple_gpio.py	bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY	2012-02-15 18:23:31 +01:00
using_record.py	record: support aligned flattening	2012-01-09 19:16:11 +01:00
wb_initiator.py	Update copyright notices	2012-03-23 16:41:30 +01:00