Florent Kermarrec 06d0806494 soc_core: set csr to 0x00000000 when there is no wishbone		2019-09-23 15:57:14 +02:00
..
boards	targets/nexys_video: generate clk100	2019-08-27 14:06:13 +02:00
build	vivado just needs to be in the path for the programmer as well	2019-09-19 20:35:55 -07:00
gen	gen/fhdl/verilog: allow single element verilog inline attribute	2019-08-28 05:24:11 +02:00
soc	soc_core: set csr to 0x00000000 when there is no wishbone	2019-09-23 15:57:14 +02:00
tools	tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example)	2019-09-12 10:21:37 +02:00
__init__.py	tools: move from litex.soc.tools to litex.tools and fix usb.core import	2019-04-20 10:44:53 +02:00