| .. |
|
__init__.py
|
add test directory with test_code_8b10b.py (from misoc)
|
2017-04-24 18:46:55 +02:00 |
|
test_axi.py
|
soc/interconnect/axi: add Wishbone2AXILite
|
2019-11-20 12:32:22 +01:00 |
|
test_bitbang.py
|
cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging
|
2019-07-05 14:26:10 +02:00 |
|
test_clock.py
|
soc/cores/clock: add CycloneVPLL.
|
2020-04-07 17:24:12 +02:00 |
|
test_code_8b10b.py
|
test: add copyright header
|
2019-06-23 23:31:11 +02:00 |
|
test_csr.py
|
soc/interconnect/csr: add initial field support
|
2019-09-13 20:01:31 +02:00 |
|
test_ecc.py
|
soc/cores: add ECC (Error Correcting Code)
|
2019-07-13 11:44:29 +02:00 |
|
test_emif.py
|
cores: add External Memory Interface (EMIF) Wishbone bridge.
|
2020-04-12 16:34:33 +02:00 |
|
test_gearbox.py
|
test: add copyright header
|
2019-06-23 23:31:11 +02:00 |
|
test_hyperbus.py
|
soc/core: simplify/cleanup HyperRAM core
|
2019-08-16 14:04:58 +02:00 |
|
test_i2s.py
|
soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores.
|
2020-02-06 17:00:04 +01:00 |
|
test_icap.py
|
soc/cores/icap: simplify ICAPBitstream (untested)
|
2019-10-01 21:30:14 +02:00 |
|
test_packet.py
|
test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer
|
2019-11-16 14:39:18 +01:00 |
|
test_prbs.py
|
test: add copyright header
|
2019-06-23 23:31:11 +02:00 |
|
test_spi.py
|
soc/cores/spi: add optional aligned mode.
|
2020-04-22 13:15:51 +02:00 |
|
test_spi_opi.py
|
soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)
|
2020-02-06 17:58:01 +01:00 |
|
test_stream.py
|
interconnect/stream: add PipeValid and PipeWait to cut timing paths.
|
2020-01-29 18:27:29 +01:00 |
|
test_targets.py
|
test/test_targets: workaround to fix travis.
|
2020-05-13 11:04:40 +02:00 |
9f941138d2