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144ee7ea9f
litex
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misoclib
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soc
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Florent Kermarrec
144ee7ea9f
soc: fix register_rom
2015-02-28 23:51:51 +01:00
..
__init__.py
soc: fix register_rom
2015-02-28 23:51:51 +01:00
cpuif.py
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
2015-02-28 11:36:15 +01:00
sdram.py
test implementation on all targets and fix issues
2015-02-28 12:04:51 +01:00