litex/misoclib
Florent Kermarrec 165a5b6760 soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000 2015-02-28 20:04:51 +01:00
..
com remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
cpu misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
mem remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
others move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future) 2015-02-28 11:51:51 +01:00
soc soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000 2015-02-28 20:04:51 +01:00
tools remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
video misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
__init__.py rename milkymist-ng to MiSoC 2013-11-09 15:27:32 +01:00