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litex/misoclib/com/liteeth/example_designs/targets
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Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
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__init__.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
base.py remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
etherbone.py litescope: move files and modify import to misoclib.tools.litescope 2015-02-28 10:33:46 +01:00
tty.py litescope: move files and modify import to misoclib.tools.litescope 2015-02-28 10:33:46 +01:00
udp.py litescope: move files and modify import to misoclib.tools.litescope 2015-02-28 10:33:46 +01:00