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https://github.com/enjoy-digital/litex.git
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1761bfba8a
litex
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misoclib
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History
Florent Kermarrec
ff51bde7f0
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
2015-05-02 16:22:40 +02:00
..
liteeth
liteeth: move mac to core
2015-05-02 16:22:35 +02:00
litepcie
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
liteusb
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
2015-05-02 16:22:40 +02:00
spi
global: pep8 (W262)
2015-04-13 17:02:59 +02:00
uart
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
__init__.py
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
gpio.py
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)
2015-05-02 16:22:33 +02:00