litex/litex
Michal Sieron 26c5a8a926 Move libbase/id.c to bios/cmd/cmd_bios.c 2021-09-16 10:42:54 +02:00
..
build build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names. 2021-09-08 16:14:58 +02:00
compat soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py. 2021-07-29 18:48:03 +02:00
gen gen/fhdl/verilog: Make DummyAttrTranslate a dict. 2021-07-15 16:48:24 +02:00
soc Move libbase/id.c to bios/cmd/cmd_bios.c 2021-09-16 10:42:54 +02:00
tools tools/litex_sim: Fix mem_map. 2021-09-13 11:33:16 +02:00
__init__.py revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00