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__init__.py
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…
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test_axi.py
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soc/interconnect/axi: add Wishbone2AXILite
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2019-11-20 12:32:22 +01:00 |
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test_bitbang.py
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cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging
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2019-07-05 14:26:10 +02:00 |
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test_clock.py
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soc/cores/clock: add CycloneVPLL.
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2020-04-07 17:24:12 +02:00 |
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test_code_8b10b.py
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test: add copyright header
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2019-06-23 23:31:11 +02:00 |
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test_csr.py
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soc/interconnect/csr: add initial field support
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2019-09-13 20:01:31 +02:00 |
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test_ecc.py
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soc/cores: add ECC (Error Correcting Code)
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2019-07-13 11:44:29 +02:00 |
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test_emif.py
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cores: add External Memory Interface (EMIF) Wishbone bridge.
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2020-04-12 16:34:33 +02:00 |
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test_gearbox.py
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test: add copyright header
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2019-06-23 23:31:11 +02:00 |
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test_hyperbus.py
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soc/core: simplify/cleanup HyperRAM core
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2019-08-16 14:04:58 +02:00 |
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test_i2s.py
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soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores.
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2020-02-06 17:00:04 +01:00 |
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test_icap.py
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soc/cores/icap: simplify ICAPBitstream (untested)
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2019-10-01 21:30:14 +02:00 |
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test_packet.py
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test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer
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2019-11-16 14:39:18 +01:00 |
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test_prbs.py
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test: add copyright header
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2019-06-23 23:31:11 +02:00 |
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test_spi.py
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soc/cores/spi: add optional aligned mode.
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2020-04-22 13:15:51 +02:00 |
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test_spi_opi.py
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soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)
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2020-02-06 17:58:01 +01:00 |
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test_stream.py
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interconnect/stream: add PipeValid and PipeWait to cut timing paths.
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2020-01-29 18:27:29 +01:00 |
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test_targets.py
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test/test_targets: remove versa_ecp3.
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2020-03-25 08:47:43 +01:00 |
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