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330d61d2bd
litex
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litex
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Florent Kermarrec
330d61d2bd
soc/add_pcie: Remove MSI workaround on Ultrascale(+) now that root cause is understood/fixed (thanks @smunaut).
2023-07-21 14:50:38 +02:00
..
build
build/lattice/common/lattice_ecp5_trellis_special_overrides: Add missing DifferentialOutput.
2023-07-17 17:08:35 +02:00
compat
compat/soc_core: Fix register_mem/rom missing imports.
2022-11-09 19:11:15 +01:00
gen
gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut.
2023-07-14 10:01:32 +02:00
soc
soc/add_pcie: Remove MSI workaround on Ultrascale(+) now that root cause is understood/fixed (thanks @smunaut).
2023-07-21 14:50:38 +02:00
tools
tools: Update to new sdcard core name.
2023-07-20 16:29:05 +02:00
__init__.py
colorer: Avoid duplication and move it to litex/gen.
2022-11-03 09:49:51 +01:00