Florent Kermarrec 5d202ddb97 test: update.		2020-06-02 13:51:48 +02:00
..
__init__.py	…
test_axi.py	soc/interconnect/axi: add Wishbone2AXILite	2019-11-20 12:32:22 +01:00
test_bitbang.py	…
test_clock.py	soc/cores/clock: add CycloneVPLL.	2020-04-07 17:24:12 +02:00
test_code_8b10b.py	…
test_csr.py	…
test_ecc.py	…
test_emif.py	cores: add External Memory Interface (EMIF) Wishbone bridge.	2020-04-12 16:34:33 +02:00
test_gearbox.py	…
test_i2s.py	Extend I2S capabilities	2020-05-20 14:31:51 +02:00
test_icap.py	…
test_packet.py	…
test_prbs.py	…
test_spi.py	soc/cores/spi: add optional aligned mode.	2020-04-22 13:15:51 +02:00
test_spi_opi.py	soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)	2020-02-06 17:58:01 +01:00
test_stream.py	interconnect/stream: add PipeValid and PipeWait to cut timing paths.	2020-01-29 18:27:29 +01:00
test_targets.py	test: update.	2020-06-02 13:51:48 +02:00