|
boards
|
platforms/netv2: add pcie pins
|
2020-01-27 08:25:57 +01:00 |
|
build
|
build/sim: allow to use environment's {C,LD}FLAGS
|
2020-02-04 17:31:31 +01:00 |
|
gen
|
gen/fhdl/verilog: fix signed init values
|
2020-01-12 22:06:35 +01:00 |
|
soc
|
soc/add_uart: fix bridge
|
2020-02-11 16:55:37 +01:00 |
|
tools
|
tools/litex_sim_new: remove
|
2020-02-11 14:05:01 +01:00 |
