litex/misoc/interconnect
Sebastien Bourdeauducq b1a90053f5 minor fixes 2015-09-29 10:19:00 +08:00
..
__init__.py interconnect: add bus/bank components from Migen 2015-09-24 20:48:18 +08:00
csr.py fix most imports 2015-09-25 18:43:20 +08:00
csr_bus.py replace flen with len 2015-09-26 18:50:11 +08:00
csr_eventmanager.py fix most imports 2015-09-25 18:43:20 +08:00
dfi.py break down sdram, improve consistency of core names 2015-09-24 15:59:55 +08:00
dma_lasmi.py fix most imports 2015-09-25 18:43:20 +08:00
lasmi_bus.py fix most imports 2015-09-25 18:43:20 +08:00
stream.py add stream, fix CPUs and more imports. simple target boots on ppro. 2015-09-26 16:44:21 +08:00
wishbone.py replace flen with len 2015-09-26 18:50:11 +08:00
wishbone2csr.py minor fixes 2015-09-29 10:19:00 +08:00
wishbone2lasmi.py fix most imports 2015-09-25 18:43:20 +08:00