Fin Maaß 53ae12ca65 litex_json2renode: correct VexRiscv variants ... corrrect the VexRiscv variants. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>		2024-06-11 10:42:36 +02:00
..
build	build/vhd2v_converter.py: pass work_package to platform	2024-06-06 15:24:20 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	sim/gtkwave: Update/fix SignalNamespace import (And make it public in fhdl/namer).	2023-11-09 10:29:43 +01:00
soc	Merge pull request #1923 from Dolu1990/vexiiriscv	2024-06-08 15:37:37 +02:00
tools	litex_json2renode: correct VexRiscv variants	2024-06-11 10:42:36 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00