Florent Kermarrec a99aa9c7fd uart: rename wishbone to bridge		2015-05-09 16:24:28 +02:00
..
targets	uart: rename wishbone to bridge	2015-05-09 16:24:28 +02:00
test	use similar names for wishbone bridges and move wishbone drivers to [core]/software	2015-05-02 16:22:30 +02:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00
make.py	lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file	2015-04-18 08:51:59 -04:00