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https://github.com/enjoy-digital/litex.git
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4990bf33c0
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).
Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
107 lines
4.3 KiB
Python
107 lines
4.3 KiB
Python
# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from migen.genlib.misc import timeline
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from migen.genlib.io import DifferentialOutput
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from litex.soc.interconnect import wishbone
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# HyperRAM -----------------------------------------------------------------------------------------
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class HyperRAM(Module):
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"""HyperRAM
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Provides a very simple/minimal HyperRAM core that should work with all FPGA/HyperRam chips:
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- FPGA vendor agnostic.
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- no setup/chip configuration (use default latency).
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This core favrors portability and ease of use over performance.
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"""
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def __init__(self, pads):
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self.pads = pads
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self.bus = bus = wishbone.Interface()
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# # #
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clk = Signal()
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clk_phase = Signal(2)
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cs = Signal()
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ca = Signal(48)
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sr = Signal(48)
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dq = self.add_tristate(pads.dq) if not hasattr(pads.dq, "oe") else pads.dq
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rwds = self.add_tristate(pads.rwds) if not hasattr(pads.rwds, "oe") else pads.rwds
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# Drive rst_n, cs_n, clk from internal signals ---------------------------------------------
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if hasattr(pads, "rst_n"):
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self.comb += pads.rst_n.eq(1)
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self.comb += pads.cs_n[0].eq(~cs)
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assert len(pads.cs_n) <= 2
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if len(pads.cs_n) == 2:
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self.comb += pads.cs_n[1].eq(1)
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if hasattr(pads, "clk"):
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self.comb += pads.clk.eq(clk)
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else:
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self.specials += DifferentialOutput(clk, pads.clk_p, pads.clk_n)
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# Clock Generation (sys_clk/4) -------------------------------------------------------------
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self.sync += clk_phase.eq(clk_phase + 1)
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cases = {}
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cases[1] = clk.eq(cs) # Set pads clk on 90° (if cs is set)
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cases[3] = clk.eq(0) # Clear pads clk on 270°
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self.sync += Case(clk_phase, cases)
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# Data Shift Register (for write and read) -------------------------------------------------
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dqi = Signal(8)
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self.sync += dqi.eq(dq.i) # Sample on 90° and 270°
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cases = {}
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cases[0] = sr.eq(Cat(dqi, sr[:-8])) # Shift on 0°
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cases[2] = sr.eq(Cat(dqi, sr[:-8])) # Shift on 180°
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self.sync += Case(clk_phase, cases)
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self.comb += [
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bus.dat_r.eq(sr), # To Wisbone
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dq.o.eq(sr[-8:]), # To HyperRAM
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]
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# Command generation -----------------------------------------------------------------------
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self.comb += [
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ca[47].eq(~self.bus.we), # R/W#
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ca[45].eq(1), # Burst Type (Linear)
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ca[16:35].eq(self.bus.adr[2:21]), # Row & Upper Column Address
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ca[1:3].eq(self.bus.adr[0:2]), # Lower Column Address
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ca[0].eq(0), # Lower Column Address
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]
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# Sequencer --------------------------------------------------------------------------------
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dt_seq = [
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# DT, Action
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(3, []),
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(12, [cs.eq(1), dq.oe.eq(1), sr.eq(ca)]), # Command: 6 clk
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(44, [dq.oe.eq(0)]), # Latency(default): 2*6 clk
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(2, [dq.oe.eq(self.bus.we), # Write/Read data byte: 2 clk
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sr[:16].eq(0),
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sr[16:].eq(self.bus.dat_w),
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rwds.oe.eq(self.bus.we),
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rwds.o.eq(~bus.sel[0])]),
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(2, [rwds.o.eq(~bus.sel[1])]), # Write/Read data byte: 2 clk
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(2, [rwds.o.eq(~bus.sel[2])]), # Write/Read data byte: 2 clk
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(2, [rwds.o.eq(~bus.sel[3])]), # Write/Read data byte: 2 clk
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(2, [cs.eq(0), rwds.oe.eq(0), dq.oe.eq(0)]),
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(1, [bus.ack.eq(1)]),
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(1, [bus.ack.eq(0)]),
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(0, []),
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]
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# Convert delta-time sequencer to time sequencer
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t_seq = []
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t_seq_start = (clk_phase == 1)
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t = 0
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for dt, a in dt_seq:
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t_seq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & t_seq_start, t_seq)
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def add_tristate(self, pad):
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t = TSTriple(len(pad))
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self.specials += t.get_tristate(pad)
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return t
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