Florent Kermarrec 5dbd8af4be liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap		2015-03-09 13:23:37 +01:00
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liteeth	liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap	2015-03-09 13:23:37 +01:00
liteusb	sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it	2015-03-02 08:36:39 +01:00
spi	com/spi: use .format in tb	2015-03-03 10:44:05 +01:00
uart	uart: pass *args, **kwargs to sim phy	2015-03-06 12:08:10 +01:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00