Commit Graph

29 Commits

Author SHA1 Message Date
Florent Kermarrec 5dbd8af4be liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap 2015-03-09 13:23:37 +01:00
Florent Kermarrec d20b9c2221 uart: pass *args, **kwargs to sim phy 2015-03-06 12:08:10 +01:00
Florent Kermarrec af66ca7bad uart: add phy autodetect function 2015-03-06 10:19:29 +01:00
Florent Kermarrec 95fa753149 liteeth: add phy autodetect function (phy can still be instanciated directly) 2015-03-06 10:10:34 +01:00
Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
Florent Kermarrec 200791c81d uart: generate ack for rx (serialboot OK with sim) 2015-03-04 00:57:37 +01:00
Florent Kermarrec 7c058a52c9 com/spi: use .format in tb 2015-03-03 10:44:05 +01:00
Florent Kermarrec 1d4dc45436 LiteXXX cores: use format in prints 2015-03-03 10:29:28 +01:00
Florent Kermarrec b305b7828a sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it 2015-03-02 08:36:39 +01:00
Florent Kermarrec f58394f6af soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :) 2015-03-01 18:25:47 +01:00
Florent Kermarrec 096e95cb59 uart: use data instead of d on endpoint's layouts (coherency with others cores) 2015-03-01 16:56:48 +01:00
Florent Kermarrec 1e6d1deae8 uart: add sim phy 2015-03-01 16:52:50 +01:00
Florent Kermarrec 649cdeb265 liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
Florent Kermarrec bd4d3cd73b uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator) 2015-03-01 12:14:34 +01:00
Florent Kermarrec c21a7956c8 liteXXX cores: remove Identifier duplication 2015-03-01 11:24:58 +01:00
Florent Kermarrec 67ca0da1d9 liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
Florent Kermarrec b32a0e6f9e liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins 2015-02-28 23:33:00 +01:00
Florent Kermarrec b34be816ec liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH) 2015-02-28 22:23:48 +01:00
Florent Kermarrec 5c43d4d091 litescope: create example design derived from SoC that can be used on all targets 2015-02-28 22:19:24 +01:00
Florent Kermarrec 0fd1b9df8d liteXXX cores: remove redefinition of get_csr_csv 2015-02-28 21:45:05 +01:00
Florent Kermarrec 5bd1ab7fa1 liteXXX cores: update README and doc 2015-02-28 21:40:59 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec 912573f5c9 liteusb: move files and modify import to misoclib.com.liteusb 2015-02-28 11:18:00 +01:00
Florent Kermarrec b647fe5823 merge liteusb 2015-02-28 11:16:16 +01:00
Florent Kermarrec 2c3e8a2804 liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:04:48 +01:00
Florent Kermarrec df0ba1b03c litescope: create example_designs directory 2015-02-28 10:42:12 +01:00
Florent Kermarrec c4ebf244a1 litescope: move files and modify import to misoclib.tools.litescope 2015-02-28 10:33:46 +01:00
Florent Kermarrec a43c555ee3 misoclib/com: add spi (only SPIMaster for now) 2015-02-28 09:43:03 +01:00
Florent Kermarrec 2c51adcd68 misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00