litex/misoclib/com
Florent Kermarrec 603b4cdc8c liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00
..
gpio global: pep8 (E302) 2015-04-13 16:47:22 +02:00
liteeth liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend 2015-04-28 18:51:40 +02:00
litepcie liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
liteusb liteusb: continue refactoring (virtual UART and DMA working on minispartan6) 2015-05-01 16:11:15 +02:00
spi global: pep8 (W262) 2015-04-13 17:02:59 +02:00
uart com/uart: add tx and rx fifos. 2015-05-01 15:59:26 +02:00
__init__.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00