Andrew Dennison f99658200e soc/cores/i2c: rewrite state machine ... * Fix READ: was reading too many bits * CLeaner transitions between states: ACK=>IDLE with scl=0. Other to IDLE with scl=1 * Now cleanly supports RESTART * conceptual support for compound commands - not exposed yet * fix tests: now appears to be I2C compliant		2024-07-20 15:45:44 +10:00
..
build	build/efinix: Add default parameter values and fix other typos.	2024-07-09 10:04:03 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	soc/cores/i2c: rewrite state machine	2024-07-20 15:45:44 +10:00
tools	tools/litex_sim: Cleanup imports.	2024-07-18 12:16:23 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00