a57f0640cc
By default, location is still automatically determined but it's now possible to
specific locations:
The following module:
class MyModule(Module, AutoCSR):
def __init__(self):
self.csr0 = CSRStorage()
self.csr1 = CSRStorage(n=0)
self.csr2 = CSRStorage(n=2)
built on a SoC with 32-bit CSR data-width will have the following CSR mapping:
- 0x00 : csr1
- 0x04 : csr0
- 0x08 : reserved
- 0x0c : csr2
|
||
|---|---|---|
| .. | ||
| __init__.py | ||
| test_axi.py | ||
| test_axi_lite.py | ||
| test_axi_stream.py | ||
| test_bitbang.py | ||
| test_clock.py | ||
| test_code_8b10b.py | ||
| test_cpu.py | ||
| test_csr.py | ||
| test_ecc.py | ||
| test_emif.py | ||
| test_fifosyncmacro.py | ||
| test_gearbox.py | ||
| test_hyperbus.py | ||
| test_i2s.py | ||
| test_icap.py | ||
| test_led.py | ||
| test_packet.py | ||
| test_prbs.py | ||
| test_spi.py | ||
| test_spi_opi.py | ||
| test_stream.py | ||
| test_timer.py | ||
| test_wishbone.py | ||