Florent Kermarrec 774a55a2aa soc_core: fix missing init on main_ram		2020-02-19 14:59:58 +01:00
..
boards	targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)	2020-02-11 17:44:24 +01:00
build	update to work with mac	2020-02-15 10:37:39 -05:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	soc_core: fix missing init on main_ram	2020-02-19 14:59:58 +01:00
tools	tools/litex_sim: use new sdram verbosity parameter	2020-02-16 16:09:06 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00