Xiretza 7a87d4e262 Fix ECP5PLL VCO frequency range ... See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5 and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".		2020-02-24 14:39:59 +01:00
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boards	targets/nexys4ddr: add optional sdcard support	2020-02-19 20:16:13 -05:00
build	build/sim: add Verilator FST tracing support.	2020-02-20 13:53:31 +01:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	Fix ECP5PLL VCO frequency range	2020-02-24 14:39:59 +01:00
tools	interconnect/axi: remove bus_name on connect_to_pads	2020-02-24 13:24:32 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00