Gwenhael Goavec-Merou aca959b059 build/efinix/common.py: ClkInput: added ClockSignal support		2024-09-19 09:12:36 +02:00
..
build	build/efinix/common.py: ClkInput: added ClockSignal support	2024-09-19 09:12:36 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	soc/interconnect/stream: Add optional CSR to Multiplexer/Demultiplexer and Crossbar module with mux and demux.	2024-09-13 19:21:26 +02:00
tools	Merge pull request #1974 from motec-research/dts_zephyr_updates	2024-09-17 14:58:51 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00