navaneeth c8a83461b4 Add initial changes to add IRQ support ... In the waveform IRQ pending seems to be going high but the call to ISR() doesn't happen.		2021-10-17 12:32:31 +05:30
..
build	fhdl/verilog: Remove blocking_assign (not used with LiteX).	2021-10-15 15:20:01 +02:00
compat	soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py.	2021-07-29 18:48:03 +02:00
gen	fhdl/verilog: Update header.	2021-10-15 15:25:23 +02:00
soc	Add initial changes to add IRQ support	2021-10-17 12:32:31 +05:30
tools	Merge pull request #1053 from rdolbeau/fb_rgb565	2021-10-08 14:15:10 +02:00
__init__.py	get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.	2021-09-28 16:27:13 +02:00