| .. |
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altera
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build: Simplify attr_translate (Now automatically defaults to None when not explicitely listed).
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2021-07-15 09:59:15 +02:00 |
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efinix
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build/efinix/efinity: Simplify get_pin_direction with direction/name already set to signals when generating the verilog.
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2021-10-14 19:12:00 +02:00 |
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gowin
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gowin/common: Add Differential Input/Output support.
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2021-09-20 14:14:06 +02:00 |
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lattice
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Update icestorm.py with u4k device, since Yosys can target it
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2021-10-08 15:20:39 -04:00 |
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microsemi
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build/microsemi/common: Cleanup MicrosemiPolarfireAsyncResetSynchronizerImpl.
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2021-07-15 10:01:52 +02:00 |
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quicklogic
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build: Add initial/minimal QuickLogic build support.
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2021-10-01 11:42:56 +02:00 |
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sim
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fhdl/verilog: Remove blocking_assign (not used with LiteX).
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2021-10-15 15:20:01 +02:00 |
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xilinx
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build/xilinx/common: Fix Ultrascale SDROutput/Input.
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2021-09-21 10:30:36 +02:00 |
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__init__.py
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litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
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dfu.py
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build/DFUProg: Allow to specify alt interface and to not reboot
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2021-06-21 16:12:55 +02:00 |
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generic_platform.py
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fhdl/verilog: Remove create_clock_domains (not used in LiteX).
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2021-10-15 15:12:30 +02:00 |
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generic_programmer.py
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build/GenericProgrammer: Add check parameter to make check optional.
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2021-06-22 11:59:38 +02:00 |
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io.py
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build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap).
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2021-09-21 08:18:06 +02:00 |
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openfpgaloader.py
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build/openfpgaloader/flash: Add external parameter to allow flashing external SPI Flash when available.
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2021-09-17 14:37:14 +02:00 |
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openocd.py
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openocd/stream: Expose chain parameter.
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2021-05-06 15:25:18 +02:00 |
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tools.py
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Compat: Add litex.compat to handle retro-compatibility on API changes and move integration/soc_sdram to it.
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2021-03-24 17:21:13 +01:00 |
3b78fd928d