Sebastien Bourdeauducq e89c66bf14 bank/csrgen: interface -> bus		2012-12-06 17:15:34 +01:00
..
actorlib	actorlib/sim: drive busy high until generator is finished	2012-12-05 16:40:12 +01:00
bank	bank/csrgen: interface -> bus	2012-12-06 17:15:34 +01:00
bus	bus/wishbone/sram: accept memories < 32 bits	2012-12-01 13:04:22 +01:00
corelogic	corelogic/roundrobin: fix request width (again)	2012-11-29 23:47:51 +01:00
fhdl	Fix various errors from new bitwidth/signedness system conversion	2012-11-29 23:36:55 +01:00
flow	Replace Signal(bits_for(... with Signal(max=...	2012-11-29 21:53:36 +01:00
pytholite	pytholite: fix bit width of selection signal	2012-11-30 17:07:32 +01:00
sim	New specification for width and signedness	2012-11-29 21:22:38 +01:00
uio	pytholite/io: support memory	2012-11-23 20:36:09 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00