Sebastien Bourdeauducq fe87221d2b dvisampler/dma: reverse slot allocation order		2013-05-09 10:51:50 +02:00
..
__init__.py	dvisampler: new DMA engine (buggy)	2013-05-08 22:31:01 +02:00
analysis.py	dvisampler: mostly working, very basic and slightly buggy DMA	2013-05-06 09:58:12 +02:00
chansync.py	chansync: bugfix	2013-05-05 15:07:57 +02:00
charsync.py	Convert to new CSR API	2013-03-30 17:28:15 +01:00
clocking.py	Remove undriven reset signals	2013-04-25 20:19:49 +02:00
common.py	dvisampler: mostly working, very basic and slightly buggy DMA	2013-05-06 09:58:12 +02:00
datacapture.py	dvisampler/datacapture: swap bit pairs	2013-05-04 20:38:50 +02:00
debug.py	dvisampler: mostly working, very basic and slightly buggy DMA	2013-05-06 09:58:12 +02:00
decoding.py	dvisampler/decoding: hold C when DE=1	2013-05-05 11:51:48 +02:00
dma.py	dvisampler/dma: reverse slot allocation order	2013-05-09 10:51:50 +02:00
edid.py	edid.py: sample SCL only every 64 clock cycles, to avoid bouncing	2013-04-12 22:48:46 +02:00