2016-04-10 08:58:07 -04:00
|
|
|
RISCV_TOOLS_PREFIX = /opt/riscv32ic/bin/riscv32-unknown-elf-
|
|
|
|
|
CXX = $(RISCV_TOOLS_PREFIX)g++
|
|
|
|
|
CC = $(RISCV_TOOLS_PREFIX)gcc
|
|
|
|
|
AS = $(RISCV_TOOLS_PREFIX)gcc
|
2015-11-03 19:12:37 -05:00
|
|
|
CXXFLAGS = -MD -Os -Wall -std=c++11
|
|
|
|
|
CCFLAGS = -MD -Os -Wall -std=c++11
|
|
|
|
|
LDFLAGS = -Wl,--gc-sections
|
|
|
|
|
LDLIBS = -lstdc++
|
|
|
|
|
|
2016-05-04 02:57:16 -04:00
|
|
|
test: testbench.vvp firmware32.hex
|
|
|
|
|
vvp -N testbench.vvp
|
2015-11-03 19:12:37 -05:00
|
|
|
|
2016-05-04 02:57:16 -04:00
|
|
|
testbench.vvp: testbench.v ../../picorv32.v
|
|
|
|
|
iverilog -o testbench.vvp testbench.v ../../picorv32.v
|
|
|
|
|
chmod -x testbench.vvp
|
2015-11-03 19:12:37 -05:00
|
|
|
|
2015-11-17 08:22:19 -05:00
|
|
|
firmware32.hex: firmware.elf start.elf hex8tohex32.py
|
2016-04-10 08:58:07 -04:00
|
|
|
$(RISCV_TOOLS_PREFIX)objcopy -O verilog start.elf start.tmp
|
|
|
|
|
$(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp
|
2015-11-03 19:12:37 -05:00
|
|
|
cat start.tmp firmware.tmp > firmware.hex
|
2015-11-17 08:22:19 -05:00
|
|
|
python3 hex8tohex32.py firmware.hex > firmware32.hex
|
2015-11-03 19:12:37 -05:00
|
|
|
rm -f start.tmp firmware.tmp
|
|
|
|
|
|
|
|
|
|
firmware.elf: firmware.o syscalls.o
|
|
|
|
|
$(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)
|
|
|
|
|
chmod -x firmware.elf
|
|
|
|
|
|
|
|
|
|
start.elf: start.S start.ld
|
|
|
|
|
$(CC) -nostdlib -o start.elf start.S -T start.ld $(LDLIBS)
|
|
|
|
|
chmod -x start.elf
|
|
|
|
|
|
|
|
|
|
clean:
|
|
|
|
|
rm -f *.o *.d *.tmp start.elf
|
2015-11-17 08:22:19 -05:00
|
|
|
rm -f firmware.elf firmware.hex firmware32.hex
|
2016-05-04 02:57:16 -04:00
|
|
|
rm -f testbench.vvp testbench.vcd
|
2015-11-03 19:12:37 -05:00
|
|
|
|
|
|
|
|
-include *.d
|
|
|
|
|
.PHONY: test clean
|
