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picorv32
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513 Commits

Author SHA1 Message Date
Clifford Wolf 3495604877 Fix indenting in wishbone code 2017-03-14 11:51:09 +01:00
Antony Pavlov a25597532d WIP: add WISHBONE testbench 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-14 09:37:05 +03:00
Antony Pavlov e59fa1dfb2 WIP: add WISHBONE interconnect support 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-14 09:37:04 +03:00
Clifford Wolf ce862f09f5 Rename "testbench_vcd" make target to "test_vcd", remove "view" 2017-03-12 10:59:22 +01:00
Clifford Wolf f33ddd3654 Fix in rvfi_mem_ handling (when compressed isa is enabled) 2017-02-27 14:21:42 +01:00
Clifford Wolf aaa9e25756 Add DEBUGNETS debug flag 2017-02-26 16:56:13 +01:00
Clifford Wolf 75830805b8 Rename "make testbench.vcd" to "make testbench_vcd" so VCD file is not removed on Ctrl-C 2017-02-21 11:17:43 +01:00
Clifford Wolf c7cc32ed95 Fix verilog code for modelsim 2017-02-17 15:23:58 +01:00
Clifford Wolf e4312b0fab Fix "mem_xfer is used before its declaration" warning 2017-02-11 12:52:18 +01:00
Clifford Wolf 42b4397390 Add scripts/presyn/ example 2017-02-09 15:15:46 +01:00
Clifford Wolf a2107ed4ff Rename RVFI ports 2017-01-27 16:12:02 +01:00
Clifford Wolf e9b6bcf9c0 Fix README toolchain build instructions 2017-01-16 13:14:28 +01:00
Clifford Wolf f975ce1e45 Fix picorv32_axi STACKADDR default value 2017-01-15 20:34:19 +01:00
Clifford Wolf 3d090cbd26 Merge pull request #28 from GuzTech/master 
Add STACKADDR parameter to picorv32_axi module
 2017-01-15 20:33:25 +01:00
Clifford Wolf 6f866fc1c8 Merge branch 'riscv-gnu-toolchain-update' 2017-01-15 16:57:22 +01:00
Oguz Meteer 510d4de1b1 Add STACKADDR parameter to picorv32_axi module 
Signed-off-by: Oguz Meteer <info@guztech.nl>
 2017-01-15 14:49:01 +01:00
Clifford Wolf 70f3c33ac8 Add newlib linker info to README file 2017-01-15 14:38:27 +01:00
Clifford Wolf 4e6cad88bc Added riscv.ld linker script (static entry point at 0x10000) 2017-01-13 17:04:22 +01:00
Clifford Wolf 8e5deeb0cb Update riscv-gnu-toolchain to git rev 914224e 2017-01-13 17:02:56 +01:00
Clifford Wolf f5d146c2f1 Added rvfi_mem interface 2016-12-20 11:49:09 +01:00
Clifford Wolf 55da6c7cd1 Some build fixes for new riscv-gnu-toolchain 2016-12-17 13:00:30 +01:00
Clifford Wolf 56dc5b3549 Improved "git cherry-pick" for riscv-binutils-gdb a5971eca338 2016-12-17 10:06:03 +01:00
Clifford Wolf 62c7b96b1c Updated riscv-gnu-toolchain to git rev 34e199d + riscv-binutils-gdb commit a5971eca338 2016-12-17 09:51:10 +01:00
Clifford Wolf b8cecc9148 Updated riscv-gnu-toolchain to git rev e3e50c5 2016-12-15 14:43:21 +01:00
Clifford Wolf 92df4b35ee Merge branch 'master' into riscv-gnu-toolchain-update 2016-12-15 14:23:20 +01:00
Clifford Wolf ef86b30b25 Fixed some linter warnings in picorv32.v 2016-12-15 14:03:27 +01:00
Clifford Wolf 0bea8428f3 Suppress iverilog warnings re parameters in "make test_synth" 2016-12-15 13:11:26 +01:00
Clifford Wolf ca5702c75f Fixed "make test_synth" 2016-12-15 13:11:26 +01:00
Clifford Wolf 72d6f6f72d Added rvfi_post_trap 2016-12-13 17:13:53 +01:00
Clifford Wolf 9d873cac92 Minor changes and build fixes for new riscv-gnu-toolchain 2016-12-10 12:09:15 +01:00
Clifford Wolf f29376ac22 assembler support for custom0 is deprecated, using cpp macros now 2016-12-09 14:48:37 +01:00
Clifford Wolf b8af714546 Added RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX Makefile variable 2016-12-09 11:47:05 +01:00
Clifford Wolf f6b009c4c9 Updated riscv-gnu-toolchain 2016-12-08 14:09:09 +01:00
Clifford Wolf 9d6fdda1fa Added cpu?_trap signals to tracecmp3.v 2016-12-03 12:48:00 +01:00
Clifford Wolf 9c494af6e1 Removed old scripts/smt2-bmc/ 2016-12-03 12:28:36 +01:00
Clifford Wolf 54a8e4b311 Fixed catching jumps to misaligned insn 2016-11-29 18:36:05 +01:00
Clifford Wolf 17c7da49f4 Renamed rvfi_opcode to rvfi_insn 2016-11-28 14:56:29 +01:00
Clifford Wolf 7fc2cbd72a More RVFI bugfixes 2016-11-27 13:46:43 +01:00
Clifford Wolf fd38f876e1 Minor RVFI bugfix 2016-11-24 15:23:33 +01:00
Clifford Wolf 117586ff19 Added RISC-V Formal Interfcae (RVFI) 2016-11-23 03:02:02 +01:00
Clifford Wolf f82af97595 Another bugfix regarding compressed ISA and unaligned insns 2016-11-18 15:36:59 +01:00
Clifford Wolf bc47b91260 Added tracecmp3 smtbmc script 2016-11-16 16:58:51 +01:00
Clifford Wolf 63af54702c Improved tomthumbtestgen 2016-10-24 16:53:34 +02:00
Clifford Wolf f79c8344fe Added scripts/tomthumbtestgen 2016-10-23 14:32:26 +02:00
Clifford Wolf 3ebf325c96 Improved README 2016-10-23 11:14:40 +02:00
Clifford Wolf 51b1a88333 Added smtbmc axicheck2, improved axicheck 2016-10-01 17:08:19 +02:00
Clifford Wolf a6f5bc4f05 Added smtbmc axicheck 2016-09-30 18:18:32 +02:00
Clifford Wolf 4101cfe810 Fixed the nontrivial compressed ISA bug found by tracecmp2 2016-09-16 13:15:21 +02:00
Clifford Wolf 197b6ffe2b Just COMPRESSED_ISA is enough to trigger the bug 2016-09-14 10:51:09 +02:00
Clifford Wolf c209c016b3 More fixes related to assertpmux checks 2016-09-13 23:21:31 +02:00