13 Commits

Author	SHA1	Message	Date
Clifford Wolf	85d8401c3d	Renamed testbench_slow_mem to testbench_nola (no look ahead)	2016-09-04 12:29:09 +02:00
Clifford Wolf	7094e61af7	Added tracer support (under construction)	2016-08-25 14:15:42 +02:00
Clifford Wolf	6c69b3812e	Using .vvp instead of .exe for iverilog executables	2016-05-04 08:57:16 +02:00
Clifford Wolf	36cdf83b3f	Added "make clean" handling of riscv-gnu-toolchain-riscv32* directories	2016-04-09 12:51:50 +02:00
Clifford Wolf	07f28068f6	Added "make check"	2015-10-14 23:26:04 +02:00
Clifford Wolf	476046c177	Minor Makefile changes	2015-07-02 11:01:21 +02:00
Clifford Wolf	997c5ce341	Added "make test_synth"	2015-06-30 01:46:25 +02:00
Clifford Wolf	44571601c1	Added "make test_sp"	2015-06-26 23:54:12 +02:00
Clifford Wolf	d4331491a8	Test firmware refactoring	2015-06-26 23:15:30 +02:00
Clifford Wolf	23b700cf73	Added basic IRQ support	2015-06-25 14:08:39 +02:00
Clifford Wolf	e84f044bc5	Major redesign of main FSM	2015-06-07 11:49:47 +02:00
Clifford Wolf	9df9d7ff90	Improved Xilinx example	2015-06-06 20:14:58 +02:00
Clifford Wolf	77ba5a1897	Initial import	2015-06-06 14:14:32 +02:00