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480 Commits

Author SHA1 Message Date
Clifford Wolf f295b900bc Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench 2017-05-27 19:58:44 +02:00
Clifford Wolf bb9ebeb9e3 Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal) 2017-05-18 17:19:08 +02:00
Clifford Wolf 436544ccab Fix decoding of C.ADDI instruction 
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts
for discussion. There was a bug in the ISA manual.
 2017-05-13 12:28:54 +02:00
Clifford Wolf cd30db3425 Add riscv-formal alu/regs blackboxing 2017-05-11 00:13:01 +02:00
Clifford Wolf bf9687028d Fix decoding of illegal/reserved opcodes as other valid opcodes 2017-05-07 21:13:46 +02:00
Clifford Wolf a13512c86a Update riscv-gnu-toolchain to git rev 4e51f26 2017-05-05 11:32:22 +02:00
Clifford Wolf 3675375072 Update riscv-gnu-toolchain to git rev 0c8f87d 2017-04-07 11:43:05 +02:00
Clifford Wolf 1b22a099f9 Merge pull request #40 from open-design/20170406.wishbone 
testbench_wb.v: unify verbose output with axi testbench
 2017-04-07 10:05:13 +02:00
Antony Pavlov 7c852571f0 testbench_wb.v: unify verbose output with axi testbench 
Unification of testbench output makes it possible to use the diff
utility for comparing testbench instruction traces.

Alas the testbench and testbench_wb traces are differ
because of interrupts, e.g.

    picorv32$ make testbench_wb.vvp
    iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v
    chmod -x testbench_wb.vvp
    picorv32$ make testbench.vvp
    iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v
    chmod -x testbench.vvp
    picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log
    picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log
    picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log
    --- /tmp/testbench.log  2017-04-06 06:56:06.079804549 +0300
    +++ /tmp/testbench_wb.log       2017-04-06 06:55:58.763485130 +0300
    @@ -850,7 +850,7 @@
     RD: ADDR=000056a0 DATA=00000013 INSN
     RD: ADDR=000056a4 DATA=fff00113 INSN
     RD: ADDR=000056a8 DATA=00000013 INSN
    -RD: ADDR=000056ac DATA=14208463 INSN  <--- testbench: no interrupt
    -RD: ADDR=000056b0 DATA=00120213 INSN
    -RD: ADDR=000056b4 DATA=00200293 INSN
    -RD: ADDR=000056b8 DATA=fe5212e3 INSN
    +RD: ADDR=00000010 DATA=0200a10b INSN  <--- testbench_wb: interrupt
    +RD: ADDR=00000014 DATA=0201218b INSN
    +RD: ADDR=00000018 DATA=000000b7 INSN
    +RD: ADDR=0000001c DATA=16008093 INSN

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-04-06 06:56:39 +03:00
Clifford Wolf 2c6cbcf72f Merge pull request #39 from open-design/20170324.wishbone 
testbench_wb.v: drop unused stuff
 2017-03-24 11:50:50 +01:00
Antony Pavlov dded496cfb testbench_wb.v: drop unused stuff 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-17 07:00:33 +03:00
Clifford Wolf 5d2ff0129a Add GIT_ENV Makefile variable (for things like http proxy settings) 2017-03-15 16:35:02 +01:00
Clifford Wolf 22ee418a74 Merge pull request #37 from open-design/20170315.testbenches 
20170315.testbenches
 2017-03-15 11:30:19 +01:00
Antony Pavlov 8e55b93541 Makefile: use automatic variables in testbench rules 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-15 07:15:31 +03:00
Antony Pavlov 1fbe25c994 testbench.v: fix whitespaces 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-15 07:15:31 +03:00
Antony Pavlov 0967a39c1d testbench_wb.v: fix output stuff 
This patch fixes wishbone testbench output issue:
'DNNE' instead of 'DONE', i.e.

    Cycle counter ......... 546536
    Instruction counter .... 69770
    CPI: 7.83
    DNNE

    ------------------------------------------------------------
    EBREAK instruction at 0x000006C4

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-15 07:10:37 +03:00
Clifford Wolf 726a76c1cc Merge branch 'wishbone' 2017-03-14 11:51:27 +01:00
Clifford Wolf 3495604877 Fix indenting in wishbone code 2017-03-14 11:51:09 +01:00
Antony Pavlov a25597532d WIP: add WISHBONE testbench 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-14 09:37:05 +03:00
Antony Pavlov e59fa1dfb2 WIP: add WISHBONE interconnect support 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-14 09:37:04 +03:00
Clifford Wolf ce862f09f5 Rename "testbench_vcd" make target to "test_vcd", remove "view" 2017-03-12 10:59:22 +01:00
Clifford Wolf f33ddd3654 Fix in rvfi_mem_ handling (when compressed isa is enabled) 2017-02-27 14:21:42 +01:00
Clifford Wolf aaa9e25756 Add DEBUGNETS debug flag 2017-02-26 16:56:13 +01:00
Clifford Wolf 75830805b8 Rename "make testbench.vcd" to "make testbench_vcd" so VCD file is not removed on Ctrl-C 2017-02-21 11:17:43 +01:00
Clifford Wolf c7cc32ed95 Fix verilog code for modelsim 2017-02-17 15:23:58 +01:00
Clifford Wolf e4312b0fab Fix "mem_xfer is used before its declaration" warning 2017-02-11 12:52:18 +01:00
Clifford Wolf 42b4397390 Add scripts/presyn/ example 2017-02-09 15:15:46 +01:00
Clifford Wolf a2107ed4ff Rename RVFI ports 2017-01-27 16:12:02 +01:00
Clifford Wolf e9b6bcf9c0 Fix README toolchain build instructions 2017-01-16 13:14:28 +01:00
Clifford Wolf f975ce1e45 Fix picorv32_axi STACKADDR default value 2017-01-15 20:34:19 +01:00
Clifford Wolf 3d090cbd26 Merge pull request #28 from GuzTech/master 
Add STACKADDR parameter to picorv32_axi module
 2017-01-15 20:33:25 +01:00
Clifford Wolf 6f866fc1c8 Merge branch 'riscv-gnu-toolchain-update' 2017-01-15 16:57:22 +01:00
Oguz Meteer 510d4de1b1 Add STACKADDR parameter to picorv32_axi module 
Signed-off-by: Oguz Meteer <info@guztech.nl>
 2017-01-15 14:49:01 +01:00
Clifford Wolf 70f3c33ac8 Add newlib linker info to README file 2017-01-15 14:38:27 +01:00
Clifford Wolf 4e6cad88bc Added riscv.ld linker script (static entry point at 0x10000) 2017-01-13 17:04:22 +01:00
Clifford Wolf 8e5deeb0cb Update riscv-gnu-toolchain to git rev 914224e 2017-01-13 17:02:56 +01:00
Clifford Wolf f5d146c2f1 Added rvfi_mem interface 2016-12-20 11:49:09 +01:00
Clifford Wolf 55da6c7cd1 Some build fixes for new riscv-gnu-toolchain 2016-12-17 13:00:30 +01:00
Clifford Wolf 56dc5b3549 Improved "git cherry-pick" for riscv-binutils-gdb a5971eca338 2016-12-17 10:06:03 +01:00
Clifford Wolf 62c7b96b1c Updated riscv-gnu-toolchain to git rev 34e199d + riscv-binutils-gdb commit a5971eca338 2016-12-17 09:51:10 +01:00
Clifford Wolf b8cecc9148 Updated riscv-gnu-toolchain to git rev e3e50c5 2016-12-15 14:43:21 +01:00
Clifford Wolf 92df4b35ee Merge branch 'master' into riscv-gnu-toolchain-update 2016-12-15 14:23:20 +01:00
Clifford Wolf ef86b30b25 Fixed some linter warnings in picorv32.v 2016-12-15 14:03:27 +01:00
Clifford Wolf 0bea8428f3 Suppress iverilog warnings re parameters in "make test_synth" 2016-12-15 13:11:26 +01:00
Clifford Wolf ca5702c75f Fixed "make test_synth" 2016-12-15 13:11:26 +01:00
Clifford Wolf 72d6f6f72d Added rvfi_post_trap 2016-12-13 17:13:53 +01:00
Clifford Wolf 9d873cac92 Minor changes and build fixes for new riscv-gnu-toolchain 2016-12-10 12:09:15 +01:00
Clifford Wolf f29376ac22 assembler support for custom0 is deprecated, using cpp macros now 2016-12-09 14:48:37 +01:00
Clifford Wolf b8af714546 Added RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX Makefile variable 2016-12-09 11:47:05 +01:00
Clifford Wolf f6b009c4c9 Updated riscv-gnu-toolchain 2016-12-08 14:09:09 +01:00