Commit Graph

15 Commits

Author SHA1 Message Date
Peter McGoron 4f85146d61 add cycle count for each iteration 2022-10-23 14:21:31 -04:00
Peter McGoron 0a435f6dc8 rename control loop verilog simulation top level module to more descriptive name 2022-10-22 01:58:37 -04:00
Peter McGoron 7971f8ea98 change heading 2022-10-22 01:55:56 -04:00
Peter McGoron 644929ef8a move documentation to other file 2022-10-22 01:55:15 -04:00
Peter McGoron 91cbf56b02 integrate adding stored dac value into rtrunc 2022-10-22 01:52:58 -04:00
Peter McGoron f361cac01b make values update on the start of the control loop, and make resets only take effect after the control loop has completed an iteration 2022-10-21 17:38:07 -04:00
Peter McGoron 12686391ee use integer saturation for dac value adjustment 2022-10-20 19:43:13 -04:00
Peter McGoron 2a300b9438 write total value to dac, not adjustment vlaue 2022-10-20 15:42:24 -04:00
Peter McGoron c42e2fe419 add write-read interface to control loop 2022-10-18 07:10:06 -04:00
Peter McGoron dc2b1fe339 move SPI master out of control loop design 2022-10-17 14:37:37 -04:00
Peter McGoron 0ef00c15d7 move simulators to the same directory of the simulated core 2022-10-17 00:45:19 -04:00
Peter McGoron 029cc53c5f some more changes 2022-10-17 00:44:30 -04:00
Peter McGoron 5125719a1f move control loop stub code to control loop rtl 2022-10-12 08:48:34 -04:00
Peter McGoron 0298299402 add everything im working on 2022-09-16 18:01:34 -04:00
Peter McGoron 01cbcb5fae add verilog SPI 2022-07-21 17:07:52 -04:00