Commit Graph

46 Commits

Author SHA1 Message Date
Peter McGoron 6b9e594b50 Successfully read PicoRV32 registers 2024-02-26 00:47:43 +00:00
Peter McGoron 88e3d15dd8 Get PicoRV32 to execute code
1. Update LiteX to 2023.12. This update adds wishbone bus addressing
   modes. Before this update, all wishbone buses used word addressing.
   For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This
   caused problems with the PicoRV32 and other modules, which are byte
   addressed.
2. Use adapter to convert between byte and word addressing. The SRAM is
   word addressed. The PicoRV32 shifts the address down by two bits to
   address the correct word. The PicoRV32 core seems to expect this.
3. Add debug register output. This is not working yet.
4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This
   seems to be simpler (combinatorial not synchronous).
5. Add some documentation.
6. Seperate config to new config file.
2024-02-25 18:58:34 +00:00
Peter McGoron 3785e3498d reorganize litex code 2024-02-22 15:35:31 +00:00
Peter McGoron f5b14d51ab picorv32 now runs: debugging outputs 2024-02-22 04:58:59 +00:00
Peter McGoron 67c670cb5c Use Decoder and custom region code for PicoRV32
The PicoRV32 SoC bus generator conflicts with the main SoC bus
generator, which causes the address locations in the generated verilog file
to be different from the set locations. This code uses custom region
classes in soc.py and the Decoder class directly, which is similar to
what the finalization of the SoC class uses, and is based on the LiteEth
code does.
2024-02-21 23:39:21 +00:00
Peter McGoron 06cf8807c3 Progress on PicoRV32
1) The PicoRV32 bus was not generated correctly. Running "finalize" on
   the bus, which is what the SoC does, does not generate the bus logic
   correctly. I don't know if  this is a bug or if the SoC bus generator is
   only meant to be used in the main SoC.

   Currently the bus logic is copied from the LiteX finalize code.

2) Add test micropython code to load code.

3) Removed BRAM. The Wishbone cache was messing with the direct
   implementation of the BRAM because the BRAM did not implement all the
   bus features correctly. LiteX has a Wishbone "SRAM" module, and despite
   it's name it can also generate BRAM if there are available BRAM. This is
   how the ROM and the startup RAM are implemented. The PicoRV32 ram
   is now using this SRAM.
2024-02-20 15:36:53 +00:00
Peter McGoron 0cfa172a89 This compiles and runson the Arty A7-100 2024-02-18 02:34:37 +00:00
Peter McGoron 4e3df09bb8 more cleanup and bug finding 2024-02-08 12:57:22 +00:00
Peter McGoron a10ad772bc boot currently loops at LiteX logo: this fixes it 2024-02-04 18:59:35 +00:00
Peter McGoron 2f92199c37 write picorv32 test code 2024-02-04 16:54:10 +00:00
Peter McGoron f7d6fbee2f remove explicit finalize, is not needed and probably out of order 2024-02-04 14:50:19 +00:00
Peter McGoron c3980f64da Correctly finalize picorv32 module
I think LiteX's SoCIORegions are reserved regions. Non-cached regions
are then placed inside these reserved regions. Each module also has
a "do_finalize" method that runs at code generation.
2024-02-04 14:47:39 +00:00
Peter McGoron 9f76e03028 Minor SPI fixes and Interconnect fix
The previous code did not properly assign all values on all cases,
and did not properly assign values (master interfaces, which are
poorly named because they are the interfaces to the master, connect
to the slave lines directly in the interconnect)
2024-02-03 00:33:52 +00:00
Peter McGoron 68ce1f4f64 Change SoC IO Region declarations
LiteX has some distinction between SoCIORegions and SoCRegions that
I don't quite get. SoCRegion has to be cached, SoCIORegion is not
cached. LiteX (Migen?) also does not allow you to reach into
submodules to read values.
2024-02-02 23:38:42 +00:00
Peter McGoron b4a8fdab56 fix misc build errors 2024-02-02 22:46:58 +00:00
Peter McGoron fbd3dcef2e picorv32 integration, take 1 2024-02-02 15:24:18 -05:00
Peter McGoron 9db87cb8ee bram: integrate into SoC using Wishbone bus, and note alignment 2024-01-21 04:38:34 +00:00
Peter McGoron 63a347a18f fix Makefile bram codegen 2024-01-20 20:43:12 +00:00
Peter McGoron 8c7f57c8e9 fix compile errors for soc.py 2024-01-20 20:35:16 +00:00
Peter McGoron 565847f7c5 merge ip changes 2024-01-20 20:28:43 +00:00
Peter McGoron 03d9d7ea8f add bram 2024-01-20 15:23:40 -05:00
Peter McGoron cd2be977bc fix SoC compile 2024-01-18 19:48:34 +00:00
Peter McGoron 0bb27e9b03 use add_constant() to modify network settings in SoC 2024-01-18 10:41:51 -05:00
Adam Mooers a9c6c1080c Added makefile formatting 2023-08-23 22:09:34 -04:00
Adam Mooers dad7e356fb Moved network from to 192.168.2 because 192.168.1 is very common 2023-08-08 23:41:28 -04:00
Adam Mooers 1243542729 Fixed spacing in assignment 2023-08-08 17:06:36 -04:00
Adam Mooers e6d88df57a csr_bitdwidth.json appears to have been superceded by mmio_descr.py 2023-08-08 17:05:47 -04:00
Adam Mooers de2f3afd1f Removed reference to non-existent file 2023-08-07 23:49:18 -04:00
Peter McGoron cf95a0fd20 refactor compiles 2023-06-28 18:49:26 -04:00
Peter McGoron 054609a459 refactor control loop interface 2023-06-28 17:38:41 -04:00
Peter McGoron 8b8e14bc7f z output reading 2023-06-27 17:50:55 -04:00
Peter McGoron 1a97dfa5aa patch control loop math to newdac widths 2023-06-27 16:01:04 -04:00
Peter McGoron 130e1775ac refactor csr2mp and docker Makefile 2023-06-26 15:49:20 -04:00
Peter McGoron f30f6f1ad5 zero scan and documentation 2023-06-23 18:15:53 -04:00
Peter McGoron 2b698fc08a rewrite pins 2023-06-23 14:51:35 -04:00
Peter McGoron addd660bf2 todo.md 2023-06-22 17:18:38 -04:00
Peter McGoron 9c294be58d add ssh key 2023-06-22 15:59:06 -04:00
Peter McGoron 5717ef59df csr to micropython 2023-06-21 18:47:52 -04:00
Peter McGoron d76c1f8ad1 documentation 2023-06-21 17:04:54 -04:00
Peter McGoron 93d9349430 rename hardware dockerfile pt 2 2023-06-20 13:14:26 -04:00
Peter McGoron 13286b940f fix misc errors 2023-06-20 13:10:12 -04:00
Peter McGoron 9c9b28116e documentation 2023-06-15 13:08:01 -04:00
Peter McGoron 2cdbc1ae9f make lawyers happy 2023-06-15 12:24:35 -04:00
Peter McGoron 65e160474b remove test clock and fix make clean failing 2023-06-15 11:22:59 -04:00
Peter McGoron 0a53be49a6 control_loop/intro.md: change directory name 2023-06-14 15:36:16 -04:00
Peter McGoron a560e51991 firmware is a form of software; gateware is the equivalent for FGPAs 2023-06-14 15:31:49 -04:00