Peter McGoron 0a435f6dc8 rename control loop verilog simulation top level module to more descriptive name		2022-10-22 01:58:37 -04:00
..
boothmul.v	add everything im working on	2022-09-16 18:01:34 -04:00
boothmul_sim.cpp	move simulators to the same directory of the simulated core	2022-10-17 00:45:19 -04:00
control_loop.v	move documentation to other file	2022-10-22 01:55:15 -04:00
control_loop_cmds.vh	write total value to dac, not adjustment vlaue	2022-10-20 15:42:24 -04:00
control_loop_sim.cpp	some more changes	2022-10-17 00:44:30 -04:00
control_loop_sim_top.v	rename control loop verilog simulation top level module to more descriptive name	2022-10-22 01:58:37 -04:00
intro.md	change heading	2022-10-22 01:55:56 -04:00
intsat.v	add everything im working on	2022-09-16 18:01:34 -04:00
intsat_sim.cpp	move simulators to the same directory of the simulated core	2022-10-17 00:45:19 -04:00