960f8682ea
Add missing parameter jtagHeaderIgnoreWidth
2023-09-25 22:15:50 +02:00
e21dc6cda5
litex add hardwarebreapoint parameter
2023-09-20 09:08:33 +02:00
acf6ad3bfd
Add doc about official RISC-V debug support
2023-09-13 14:56:07 +02:00
213e4b863a
litex add -expose-time
2023-09-12 10:40:45 +02:00
220a2733be
litex privileged debug stop time now connect to clint
2023-09-08 16:47:54 +02:00
ff922ec601
Merge branch 'litex-privileged-debug' into dev
2023-09-08 16:26:38 +02:00
9fd127d6d9
fix naming
2023-09-08 16:26:23 +02:00
73733dd8b1
litex privileged debug
2023-09-08 16:00:59 +02:00
3739b9ac88
plic update
2023-08-29 08:58:48 +02:00
5ef1bc775f
SpinalHDL 1.9.3
2023-08-16 09:59:21 +02:00
badf13be02
SpinalHDL 1.9.2
2023-08-10 09:02:15 +02:00
1721ac253e
SpinalHDL 1.9.0
...
Merge branch 'dev'
2023-07-21 17:45:18 +02:00
fd0f23abb6
Merge branch master into dev
2023-07-11 04:19:06 +08:00
1746af1cfe
Fix #352 GenCustomInterrupt demo
2023-07-11 04:16:21 +08:00
5860dc2321
Update DBusSimplePlugin.scala
2023-06-16 10:07:24 +01:00
d95c9356fa
Merge pull request #350 from AdDraw/master
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Add cmd halfPipe function to DBusSimpleBus
2023-06-16 07:47:40 +01:00
7f647f9d8d
Update DBusSimplePlugin.scala
2023-06-16 08:47:18 +02:00
050b4d8c62
Add halfPipe function to DBusSimpleBus
2023-06-15 22:57:20 +02:00
760a0fced5
Update SpinalHDL
2023-05-23 18:18:57 +02:00
b81029f619
fix fpu underflow rounding ( #343 )
2023-05-16 16:50:38 +01:00
ba6dcb1789
Add a few privSpec tests
2023-04-27 14:56:41 +02:00
8fc5f35d29
DBusCachedPlugin now provide writesPending signal
2023-04-24 13:13:55 +02:00
7649157946
d$ toBmb increase aggregation timer
2023-04-13 16:52:20 +02:00
051080e060
CsrPlugin now implement dummy HPM
2023-04-13 16:51:44 +02:00
d966c4efe1
fix #328 medeleg EBREAK added
2023-04-10 13:02:51 +02:00
c52433575d
Merge pull request #327 from andreasWallner/remove_sbt_assembly
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Remove sbt-assembly dependency
2023-04-08 07:14:48 +01:00
d8f6f28020
Remove sbt-assembly dependency
...
The plugin is not used in the VexRiscV build and causes issues for users
since repo.scala-sbt.org seems to be down/sunset/?.
See also https://github.com/sbt/sbt/issues/7202
Updating the dependency would also have been an option, but since it's not
used removal is easier.
2023-04-07 18:59:20 +02:00
320867e135
sync
2023-04-04 18:11:33 +02:00
f3d7442e2d
Merge remote-tracking branch 'origin/dev'
2023-04-04 11:50:11 +02:00
95e61a7951
Revert CfuPlugin
2023-04-04 11:47:49 +02:00
cb0bacfce9
implement dummy pmp as 1.10 spec says
2023-03-31 10:12:52 +02:00
b4d5a315cf
CsrPlugin implement dummy pmp if no pmp is there
2023-03-31 10:11:53 +02:00
9c2e05cce0
Ensure that fence.i wait d$ inflight write and reschedule the next instruction
2023-03-29 14:56:53 +02:00
e357420d11
CsrPluginConfig more var
2023-03-29 11:10:51 +02:00
f0bb6e94e4
SpinalHDL 1.8.1 / Merge branch 'dev'
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# Conflicts:
# src/main/scala/vexriscv/plugin/CsrPlugin.scala
2023-03-27 10:02:14 +02:00
a33380894c
sync
2023-03-27 09:57:55 +02:00
e754c5c3a0
cleanup IBusDBusCachedTightlyCoupledRam
2023-03-27 08:23:32 +02:00
eeb65ed1c0
VexRiscvBmbGenrator now use relaxedReset
2023-03-24 08:39:07 +01:00
c69852c0cc
ClockDomainResetGeneratorIf introduction
2023-03-23 16:57:10 +01:00
8195bec788
privSpec now check FPU dirty flag
2023-03-23 11:24:38 +01:00
8c5071ce42
VexRiscvSmpCluster fullCsr improvement
2023-03-23 08:53:41 +01:00
b01490b5f3
Implement counteren (1.10+ spec)
2023-03-23 08:53:10 +01:00
570720fdd8
Cfu add enableInit option
2023-03-22 17:13:47 +01:00
0e59a56bd1
add privSpec test
2023-03-22 16:25:23 +01:00
bba022b746
fix a few csr related WARL (minor)
2023-03-22 16:25:03 +01:00
385a195d16
few more var parameters
2023-03-22 12:58:43 +01:00
a755d839b3
Add VexRiscvSmpClusterGen csrFull (wip)
2023-03-22 11:07:18 +01:00
5b47564024
A few plugins config are now var
2023-03-22 11:06:56 +01:00
4972a27ae9
More verbose main.cpp on failure, fix C.ADDSP regfile initialisation
2023-03-22 11:06:23 +01:00
0aa8cb11e0
BranchPlugin do not use casez anymore
2023-03-15 17:43:44 +08:00
StaubRobin
Dolu1990
AdDraw
Andreas Wallner