Commit Graph

7 Commits

Author SHA1 Message Date
Unai Martinez-Corral ce156d29f7 s/SymbiFlow/F4PGA/
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
2022-02-21 18:39:03 +01:00
Unai Martinez-Corral f092b2fa9e conf: add logo and favicon; use '_static'
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
2022-02-21 17:49:38 +01:00
Unai Martinez-Corral a0a406e301 use intersphinx instead of adding submodules
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
2022-02-10 04:14:26 +01:00
Robert Winkler 747740a6b1 Add information about inverter logic in techmaps
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-09-28 11:30:12 +02:00
Robert Winkler 2db5d5beb6 Add technology mapping description
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-09-28 11:25:53 +02:00
Tomasz Michalak 391951918b Replace VPR abstract with official VPR documentation
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-09-25 21:50:21 +02:00
Robert Winkler c73f9c8c96 Add SymbiFlow toolchain description
Describe the synthesis and place and route process.
Add short description of Yosys synthesis tool.

Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com>
2019-09-25 21:50:21 +02:00